1. Field of the Invention
Embodiments of the present invention relate to a method of manufacturing a semiconductor device. More particularly, embodiments of the present invention relate to a method of forming fine metal semiconductor patterns with a reduced pitch therebetween using a damascene process.
2. Description of the Related Art
In general, manufacturing of highly integrated semiconductor devices may require formation of a large number of miniaturized elements, e.g., semiconductor patterns, and integration thereof within a small area. Conventional formation of semiconductor patterns, e.g., interconnect patterns, may be achieved via, e.g., photolithography and film patterning. For example, semiconductor patterns may be film patterned by etching a conductive film, e.g., a tungsten (W) film, via embossed hardmask patterns. Integration of the semiconductor patterns within a small area may require a reduced pitch therebetween, i.e., a reduced sum of a width of a single semiconductor pattern and a width of a single gap between adjacent semiconductor patterns.
However, reducing a pitch between adjacent semiconductor patterns may be limited when using photolithography due to resolution restrictions. Further, reducing a pitch between adjacent semiconductor patterns, e.g., interconnect patterns, when using, e.g., tungsten, film patterning may be limited due to generation of a resistance capacitance (RC) delay by a coupling capacitor. Accordingly, attempts have been made to form semiconductor patterns via patterning of copper (Cu) due to its low resistance, as compared to tungsten and/or aluminum, and relative stability to electro-migration (EM) and/or stress-migration (SM).
Despite the reliability imparted to a semiconductor devices having copper semiconductor patterns due to the low resistance thereof, formation of such semiconductor patterns may be complex because of poor etch characteristics of the copper. More specifically, formation of copper semiconductor patterns may require film patterning via a damascene process instead of direct etching through embossed masks. For example, negative patterns may be formed, e.g., with a silicate mask, in an insulating film, followed by filling of the negative patterns with copper.
However, formation of a plurality of negative patterns with a fine pitch therebetween, e.g., about several nanometers to about several tens of nanometers, in an insulating film by way of a damascene process may be complex even when double patterning is used. For example, a reduced pitch between adjacent negative patterns may provide uneven and/or inaccurate pattern profiles, and may potentially trigger a pattern collapse and/or electrical failures. Further, it may be difficult to form simultaneously negative patterns with varying dimensions, e.g., fine patterns for a cell array region and larger patterns for circuit elements in peripheral regions, in a single insulating film. Accordingly, there exists a need for a method of forming a plurality of fine semiconductor patterns with reduced pitch therebetween by way of a damascene process.